fpga-debugging
On-chip debugging skill with ILA, VIO, and related FPGA debug tools
DeepseekModel
官方收录技能
质量 优秀 · 90
v1.0.0
获取
https://deepseekmodel.com/api/download.php?id=a5c-ai-babysitter-library-specializations-fpga-programming-skills-fpga-debugging-skill-md&format=skill
下载 .skill
标准格式，含 system_prompt 与 model_config，导入任意 Agent 框架即可使用
.skill 文件中 system_prompt 字段的实际内容。
name fpga-debugging description On-chip debugging skill with ILA, VIO, and related FPGA debug tools allowed-tools ["Read","Write","Edit","Glob","Grep","Bash"] graph {"domains":["domain:embedded-systems"],"specializations":["specialization:fpga-programming"],"skillAreas":["skill-area:hdl-design","skill-area:fpga-synthesis"],"roles":["role:embedded-engineer"]} FPGA Debugging Skill Overview Expert skill for on-chip debugging using Integrated Logic Analyzer (ILA), Virtual I/O (VIO), and related debug infrastructure for FPGA designs. Capabilities Insert Integrated Logic Analyzer (ILA) probes Configure trigger conditions and capture depth Design Virtual I/O (VIO) debug interfaces Analyze captured waveforms Use ChipScope/SignalTap for debugging Debug timing and functional issues in hardware Remove debug logic for production builds Configure JTAG and debug hub Target Processes fpga-on-chip-debugging.js functional-simulation.js design-for-testability.js Usage Guidelines ILA Insertion Identify critical signals to probe Consider capture depth vs. resource usage Group related signals in single ILA Use mark_debug attribute for HDL signals Configure appropriate data and trigger widths Trigger Configuration Use basic triggers for simple conditions Apply advanced triggers for complex patterns Combine triggers with AND/OR logic Configure trigger position in capture window Use storage qualification for efficient capture VIO Usage Create debug control interfaces Inject test patterns dynamically Override internal signals Monitor status in real-time Useful for bring-up and characterization Debug Infrastructure Connect debug hub to JTAG Configure clock domain for debug logic Plan for multiple ILA instances Consider debug access port routing Document debug signal mapping Production Considerations Use ifdef guards for debug logic Create debug and release build flows Minimize debug impact on timing Remove debug before final release Maintain debug build configurations Dependencies Debug tool CLI (hw_server, etc.) JTAG connectivity Vendor debug IP knowledge
Agent 识别该技能的关键词，点击任意一个即可复制。
该技能未提供触发词。
下载的 .skill 包内含以下字段。
| 字段 | 说明 |
|---|---|
| format | 格式标识（skill/v1） |
| skill_id | 技能唯一 ID |
| name | 技能名称 |
| version | 版本号 |
| description | 技能描述 |
| category | 所属分类（数组） |
| trigger_words | 触发词列表 |
| tags | 标签列表 |
| source | 来源标识 |
| source_url | 来源链接（本页地址） |
| exported_at | 导出时间（每次下载生成） |
| system_prompt | 系统提示词正文 |
| model_config | 模型参数：provider / model / temperature / max_tokens / top_p |
| examples | 示例 |
| install_guide | 各平台导入说明（Coze / Dify / Claude / 自定义框架） |
